EE 4755, EE 4702, EE 7722
EE 4755 – Digital Logic Design Using Hardware Description Languages
Room: PFT 2241
In this course, students use industrial electronic design automation (EDA) tools to describe, simulate, and synthesize medium-complexity digital circuits. Circuits are described using the SystemVerilog hardware description language and are then simulated and synthesized using Cadence EDA tools provided as part of their university program. Students' design skills are developed by having them estimate their circuits' cost and performance and verifying these expectations against synthesized ground truth.
Industry tools are used by class participants to complete assignments, provided through the Cadence university program. These include the Xcelium suite for design and simulation and the Genus suite for synthesis.
Typical Assignments
In first assignments, students familiarize themselves with using the software; the design goal itself is usually modest. For example, 2023 Homework 1 involved an ASCII character representing a radix-r digit being converted to its numerical value. Students entered a design using a text editor (eMacs or the editor of their choice), used a SystemVerilog simulator (Xcelium xmrun) to verify their design, and a pre-scripted synthesis program (Genus) to obtain the cost and performance of their design.
In the next assignments, students complete combinational designs using more advanced techniques, including iteration and recursion to describe hardware. These assignments build understanding of circuit structure and how to make cost and performance tradeoffs.
In mid- to late-semester assignments, students must complete sequential designs. These exercise students' ability to understand, describe, and debug sequential designs. Here, debugging tools, Cadence SimVision in particular, are an important part of completing the assignment.
In all cases, students use industrial tools and are referred to those tools' documentation and the SystemVerilog language standard document (students can also use a digital design textbook to help make the transition).
Equipment used for this course was provided in part by grants from the Louisiana Board of Regents.
EE 4702 – GPU Programming
Room: PFT 2241
In this course, students learn low-level programming of GPU accelerators for real-time 3D animation. The emphasis is on understanding the GPU hardware, and with this understanding, programming it to achieve performance goals. Host programming is in C++ using the Vulkan API; GPU programming is in the OpenGL Shading Language.
Students use Vulkan and OpenGL Shading Language, which are both widely utilized in industry, and, in particular, are used where performance is important. Host coding is done in C++ and compiled using the GNU toolchain; it’s also used for projects with a significant game-physics component in conjunction with NVIDIA CUDA. Debugging is done through gdb, a part of the GNU toolchain. The GNU toolchain is also widely employed in industry, so students' experience with it is relevant.
Students use computers equipped with recent generation GPUs.
Typical Assignments
In a typical assignment, students must write or modify code to achieve a performance objective by using a particular language functionality, data organization, or coding technique. For example, students might start with a sphere displaying a pattern and will need to add shader code so that the pattern appears to be peeling off as though it were composed of poorly applied stickers.
Equipment used for this course was provided in part by grants from the Louisiana Board of Regents.
EE 7722 – GPU Microarchitecture
Room: PFT 2241
In this course, students learn the inner workings of computational accelerators—including GPUs—and how they are applied to important workloads. The course starts with a description of NVIDIA GPUs, with programming assignments in CUDA. In recent semesters, the assignments have covered workloads of interest related to neural networks. After covering standard existing products, the course moves on to novel and proposed accelerator designs, including the Google TPU and various academic ideas for computational acceleration.
The programming component uses CUDA, a widely employed language for computational accelerators and the design of NVIDIA GPUs, which are extensively used. Code analysis is done at the machine language (SASS) level and using hardware performance counters (via CUPTI), both important industrial practices. After NVIDIA GPUs, other "ground truth" systems are covered, including Google's TPU series. The course also covers new (industrial product) or proposed (academic idea) designs which can vary in terms of practicality. For assignments, students use recent model GPUs. In the Spring 2023 semester, that included RTX 4090 and H100 (Hopper) GPUs.
Typical Assignments
In a typical assignment, students need to modify given code to achieve an objective. Oftentimes, that entails modifying data arrangement, data to thread assignment an iteration order, or using new coding techniques or features. Programs are instrumented and involve self-report information, such as data throughput, instruction throughput, cache behavior, and overall performance normalized to ideal execution based on certain assumptions (such as number of floating point operations needed and device FP bandwidth).
Equipment used for this course was provided in part by grants from the Louisiana Board of Regents.
ECE Linux Student Workstation Laboratory
The ECE Linux Student Workstation Laboratory provides computers for a number of undergraduate and graduate courses.
Primary Location – Room 2241 Patrick F. Taylor Hall (the back)
Eight Workstations
OS: Red Hat Enterprise Linux 9.2
CPU: Intel Xeon Silver 4316: Ice Lake, twenty core, AVX 512
GPU: Nvidia RTX 4090